|
|
Syllabus:
CSE 255
Microprocessors |
|
SEMESTER: Fall 2000
CREDIT HOURS: 4.0 (includes 1 credit hour for CSE 255 lab)
You will receive a single, combined grade for lecture and laboratory.
REQUIRED TEXT: "Microprocessor Systems Design: 68000 Hardware,
Software and Interfacing," Alan Clements, PWS Publishing Company, 1997,
ISBN 0-534-94822-7.
Lectures will frequently include material not found in the textbook.
You are responsible for all material discussed in class, assigned in the
text, or covered in lab.
USEFUL REFERENCES:
NAU's Cline Library contains a number of books on assembly language
programming, architecture, and interfacing of the 68000 microprocessor.
COURSE PREREQUISITES:
The successful completion of either CSE 122 (C programming) or 126 (Java
programming) and CSE 247 (Intro to Digital Logic) with grades of C or
better are required.
COURSE DESCRIPTION:
Theory, design, and applications of microprocessors and microprocessor-based
computers and systems; programming techniques for microcomputers; commercial
microprocessors and semiconductor memory systems.
COURSE GOAL:
To achieve a good understanding of microprocessors at both the hardware
and software levels.
ACCREDITATION BOARD FOR ENGINEERING AND TECHNOLOGY
ABET Professional Requirements contribution of this course: 4 credits
of engineering science.
This course is designed to meet the following ABET learning objectives
and outcomes:
Objective 1: Students will be able to use knowledge and skills in computer
science to support their professional activities.
Outcome 1.5: Students acquire knowledge of computer organization and architecture.
(H)
Objective 3: Students will be able to function professionally with strengths
in design, problem solving, communications, and teaming.
Outcome 3.2: Students learn to identify, formulate, and solve computer
science and engineering problems. (M)
Outcome 3.3: Students learn to use the techniques, skills, and modern
engineering tools necessary for computer science and engineering practice.
(M)
(L) = light emphasis, (M) = moderate emphasis, (H) = heavy emphasis
TOPICS AND OBJECTIVES (E = Exposure, U = Utility, M = Mastery)
| Overview of computer architecture |
E |
| Register transfer logic, arithmetic logic unit (ALU) |
U |
| Instruction fetch/execute cycle |
U |
| 68000 assembly language programming |
M |
| Stacks, stack frames, parameter passing |
M |
| Memory interfacing to 68000 |
M |
| Address decoding |
M |
| Memory-mapped I/O |
U |
| Interrupts and exceptions |
U |
| Other commercially-available processors |
E |
COURSE GRADING:
The course grade will be based upon two mid-term exams, homework, quizzes,
laboratory assignments, and a comprehensive final exam. Grades will be
based not only on technical content but also on presenting your homework
and lab reports in a well organized, neat, clear, professional manner
using standard technical terms and symbols.
| Exam 1 |
100 points |
@ approx. the 6th week
ABET outcomes 1.5 (H), 3.2 (M), 3.3 (L) |
| Exam 2 |
100 |
@ approx. the 11th week
ABET outcomes 1.5 (H), 3.2 (M), 3.3 (L) |
| Final Exam |
150 |
ABET outcomes 1.5 (H), 3.2 (M), 3.3 (L) |
| Quizzes |
50 |
10 points each, only the best five scores count |
| Homework |
100 |
|
| Laboratory |
150 |
ABET outcomes 3.2 (M), 3.3 (H) |
| Total |
650 |
|
Final grades will be determined by the following percentages:
A = 90+, B = 80-89, C = 70-79, D = 60-69,
F = below 60
At the instructor's discretion, grading thresholds may be relaxed slightly.
Assignments are not accepted late. No makeup exams will be given except
by prior arrangement in exceptional, unavoidable, emergency situations.
Please contact me immediately if such a situation arises.
QUIZZES:
During at least 6 regular class periods throughout the semester, a short
quiz will be given. These quizzes are worth 10 points each, but only your
5 highest quiz scores will count toward your final grade. The remainder
will be dropped. Quizzes will not be announced in advance. Also, they
may occur anytime during the class period: beginning, middle, or end.
If you are not present when a quiz is given, you will receive a zero for
that quiz. No make-up quizzes will be allowed under any circumstances.
Suggested strategy: keep current and be ready.
ACADEMIC DISHONESTY:
Incidents of cheating or plagiarism are treated quite seriously. The NAU
policy on academic dishonesty in Appendix G of the 1998-2000 Student Handbook
will apply.
NEED EXTRA HELP?
I want you to succeed in this course! I'm willing to help you in any reasonable
way I can. If you're beginning to have difficulty, please contact me before
the situation deteriorates.
STANDARD UNIVERSITY POLICIES also apply:
· Safe Environment
· Students with Disabilities
· Accommodation of Religious Observance and Practice
· Institutional Review Board (use of human subjects)
· Classroom Management
· Academic Integrity
· Evacuation
LECTURE OUTLINE
This schedule may change somewhat.
| Week |
Topic |
Text Reference |
| 1 |
Course overview, basic computer architecture |
lecture, Chap. 1 |
| 2 |
Register transfer logic, ALU design, instruction cycle |
lecture |
| 3 |
68000 registers, assembler directives, simple instructions |
lecture, 2.1 - 2.4 |
| 4 |
Addressing modes, status register, conditional branch |
lecture, 2.4 - 2.7 |
| 5 |
Stacks, subroutines, simple parameter passing |
3.1 - 3.2 |
| 6 |
Stack frames, Exam 1 |
3.2 |
| 7 |
68000 hardware lines, 68000 read cycle |
4.1 - 4.2 |
| 8 |
68000 write cycle, bus handshaking |
4.2, lecture |
| 9 |
Full and partial address decoding |
5.1 - 5.2 |
| 10 |
RAM interfacing, SRAM vs. DRAM |
5.3 |
| 11 |
Interrupts, Exam 2 |
6.1 |
| 12 |
Exception handling, assembly and C |
6.1 - 6.4, 3.3 |
| 13 |
Execution timing, A/D and D/A |
lecture |
| 14 |
Modern microprocessors and features |
lecture |
| 15 |
Wrapup, Review |
lecture |
| 16 |
Final Exam: 10:00 - 12:00, Wednesday, Dec. 13, 2000 |
|
|
Copyright 1998 Northern Arizona University
