NAU Electrical Engineering
Dr. Phillip A. Mlsna






Syllabus: EE 215
Microprocessors

SEMESTER: Spring 2004

CREDIT HOURS: 4.0 (includes 1 credit hour for EE 215 lab)

You will receive a single, combined grade for lecture and laboratory.

CLASS TIMES
Lecture (common to both sections): T-Th, 9:35-10:50, room 206
Lab section 1 (course #6747 ): Tuesday, 2:20-4:50, room 265, taught by Dr. Mlsna
Lab section 2 (course #8345 ): Thursday, 2:20-4:50, room 265, taught by Dr. Guo

REQUIRED TEXT: "Microprocessor Systems Design: 68000 Hardware, Software and Interfacing," Alan Clements, PWS Publishing Company, 1997, ISBN 0-534-94822-7.

Lectures will frequently include material not found in the textbook. You are responsible for all material discussed in class, assigned in the text, or covered in lab.

USEFUL REFERENCES:
NAU's Cline Library contains a number of books on assembly language programming, architecture, and interfacing of the 68000 microprocessor. You can also find a variety of information on the web about both the 68000 and the PIC processors.

COURSE PREREQUISITES:
1. The successful completion of CS 122 (C programming), CS 126 (Java programming), or EE 222 (Matlab and C programming) with a grade of C or better.
2. The successful completion of EE 210 or CSE 247 (Intro to Digital Logic), with a grade of C or better.
Providing false information about prerequisites (i.e. incorrectly claiming that you have met the prerequisites) will be considered academic dishonesty.

COURSE DESCRIPTION:
Theory, design, and applications of microprocessors and microprocessor-based computers and systems; programming techniques for microcomputers; commercial microprocessors and semiconductor memory systems.

COURSE GOAL:
To achieve a good understanding of microprocessors at both the hardware and software levels.

ACCREDITATION BOARD FOR ENGINEERING AND TECHNOLOGY
ABET Professional Requirements contribution of this course: 4 credits of engineering science.

This course is designed to meet the following ABET learning objectives and outcomes:

Objective 1: Students will be able to use knowledge and skills in electrical engineering to support their professional activities.
Outcome 1.5: Students acquire knowledge of computer organization and architecture. (H)

Objective 3: Students will be able to function professionally with strengths in design, problem solving, communications, and teaming.
Outcome 3.2: Students learn to identify, formulate, and solve computer engineering problems. (M)
Outcome 3.3: Students learn to use the techniques, skills, and modern engineering tools necessary for engineering practice. (M)

(L) = light emphasis, (M) = moderate emphasis, (H) = heavy emphasis


TOPICS AND OBJECTIVES (E = Exposure, U = Utility, M = Mastery)

Overview of computer architecture E
Register transfer logic, arithmetic logic unit (ALU) U
Instruction fetch/execute cycle U
68000 assembly language programming M
Stacks, stack frames, parameter passing M
Memory interfacing to 68000 M
Address decoding M
PIC processor architecture, assembly programming M
Memory-mapped I/O U
Interrupts and exceptions U


COURSE GRADING:
The course grade will be based upon two mid-term exams, homework, quizzes, laboratory assignments, and a comprehensive final exam. Grades will be based not only on technical content but also on presenting your homework and lab reports in a well organized, neat, clear, professional manner using standard technical terms and symbols.

Pre-req Exam 50 points first week
Exam 1 100 @ approx. the 6th week
ABET outcomes 1.5 (H), 3.2 (M), 3.3 (L)
Exam 2 100 @ approx. the 11th week
ABET outcomes 1.5 (H), 3.2 (M), 3.3 (L)
Final Exam 150 ABET outcomes 1.5 (H), 3.2 (M), 3.3 (L)
Quizzes 50 10 points each, only the best five scores count
Homework 100  
Laboratory 150 ABET outcomes 3.2 (M), 3.3 (H)
Total 700  

Final grades will be determined by the following percentages:
A = 90+, B = 80-89, C = 70-79, D = 60-69, F = below 60

At the instructor's discretion, grading thresholds may be relaxed slightly.

LATE WORK:
Assignments are not accepted late. No makeup exams will be given except by prior arrangement in exceptional, unavoidable, emergency situations. Please contact me immediately if such a situation arises.

QUIZZES:
During at least 6 regular class periods throughout the semester, a short quiz will be given. These quizzes are worth 10 points each, but only your 5 highest quiz scores will count toward your final grade. The remainder will be dropped. Quizzes will not be announced in advance. Also, they may occur anytime during the class period: beginning, middle, or end. If you are not present when a quiz is given, you will receive a zero for that quiz. No make-up quizzes will be allowed under any circumstances. Suggested strategy: keep current, attend class, and be ready.

ACADEMIC DISHONESTY:
Incidents of cheating or plagiarism are treated quite seriously. The NAU policy on academic dishonesty in Appendix G of the current Student Handbook will apply. You are expected to adhere to the highest standards of professional ethics.

NEED EXTRA HELP?
I want you to succeed in this course! I'm willing to help you in any reasonable way I can. If you're beginning to have difficulty, please contact me before the situation deteriorates.

STANDARD UNIVERSITY POLICIES also apply:
· Safe Working and Learning Environment
· Students with Disabilities
· Accommodation of Religious Observance and Practice
· Institutional Review Board (use of human subjects)
· Classroom Management
· Academic Integrity
· Evacuation

LECTURE OUTLINE
This schedule and list of topics is subject to change.

Week Topic Text Reference
1 Course overview, basic computer architecture lecture, Chap. 1
2 Register transfer logic, ALU design, instruction cycle lecture
3 68000 registers, assembler directives, simple instructions lecture, 2.1 - 2.4
4 Addressing modes, status register, conditional branch lecture, 2.4 - 2.7
5 Stacks, subroutines, simple parameter passing 3.1 - 3.2
6 Stack frames, Exam 1 3.2
7 PIC processor architecture, registers, assembly language lecture
8 68000 hardware lines, 68000 read cycle 4.1 - 4.2
9 68000 write cycle, bus handshaking 4.2, lecture
10 Full and partial address decoding 5.1 - 5.2
11 RAM interfacing, SRAM vs. DRAM 5.3
12 Exam 2, Interrupts, Exception handling 6.1 - 6.4
13 More on the PIC processor lecture
14 68000 execution timing, caches lecture
15 Wrapup, Review lecture
16 Final Exam: Tuesday, May 4, 2004, 7:30-9:30 a.m.  
 

A workbench used in the laboratory portion of this course.
We now have newer computers than these.

 

An important lab tool, the mixed-signal oscilloscope


Published on Thu, Jan 8, 2004
Send E-Mail to Dr. Mlsna
NAU Logo Copyright 1998, 2004 Northern Arizona University
ALL RIGHTS RESERVED